1. Field of the Invention
The present invention relates to simulating a receive data eye of a high-speed serial interconnect and, more particularly, to finding a worst-case data and jitter pattern to minimize the size of a receiver's data eye.
2. Background Art
In designing a high-speed serial interconnect system, the distortion that a channel will introduce in a signal moving from one chip to another chip needs to be characterized. An example of such a system 10 is shown in FIG. 1, which includes a transmit die 12, a receive die 14 and a channel, generally indicated at 16, there-between. As used herein, “channel” is defined as the electrical connections from a transmit chip's die pad to another chip's die pad. The channel can include, at the transmit end, the physical package, any vias to enable the pin escape from the package to the printed circuit board (PCB), the physical etch on the PCB, any connectors used, and the mirror of these are provided at the receive end. The channel 16 can be considered a low-pass filter that applies a filtering function to a digital data stream. Thus, as the data rate increases, amplitude is reduced and data is shifted in time. It is thus important to know how much signal there is left by the time the signal arrives at the receiver.
If a data stream has a highly variable transition density, there are numerous complicated patterns that exist in the data. The transition density is the number of times the logic state for a bit changes within a certain number of bits. For example, in an 8B/10B coding, a maximum period of time without having a transition is five bit times. Thus, a worst-case transition density is one in five. In an un-encoded bus, the transition density can be much worse, e.g., 1 in 500. As the data rate increases, a propagation delay in bit times increases through the channel. Thus, since the propagation delay is multiple bit times (e.g., time it takes to transmit one bit), history of the data that was sent down the transmission line must be considered to determine what an arbitrary bit will do at the receiver (e.g., the analog voltage is a function of what was previously sent). The higher the data rate and the longer the channel, the more bits there are in transit that can interfere with the data pattern. Since the channel functions as a low pass filter, high frequency data patterns will get attenuated more than low frequency data patterns. This is one part of the history that impacts the size of the data eye. For example, if there is a long string of 0s and then a single 1 bit, the amplitude of the 1 bit would be compromised by the long string of 0s before it. Thus, a designer needs to know whether there is a large enough analog voltage to ensure that it can be received correctly.
Designers of high-speed serial systems must consider effects, as discussed above, of Inter-symbol Interference (ISI) caused by high frequency attenuation of the channel, and effects of reflections occurring at the receiver that cause reflected signals to travel towards the transmitter, with the transmitter reflecting the signals back to the receiver. These reflected signals interfere at some future time with a signal that is transmitted through the channel. Crosstalk is another effect that must be considered by designers, where, in a channel, there is a victim and on either side of the victim there are aggressors. The pattern on the aggressors couples into the victim pattern and thus can affect the size of the data eye of a bit. The victim contains the differential signals that are being sampled, and the aggressor channels contain differential signals that are adjacent to the measured signals but are coupled to the measured signals when the differential signal of an aggressor switches. The aggressor signals can occur in such a phase to reduce the amplitude of the measured signals. Finally, since the transmitter is not ideal, jitter of the transition time of a bit can be generated on its transmitted data pattern that can occur uncorrelated to the actual data pattern. Since the channel is a low-pass filter, if the jitter occurs in such a way that a bit time is compressed, it would get attenuated more by the channel than a bit time that is of a nominal width.
With above-mentioned effects occurring simultaneously, there is difficulty in determining size of the worst-case data bit in terms of time and amplitude. For a typical channel in a PCB environment, the settling time can be up to 40 bit times (e.g., the time for most of the energy of a pulse to decay away). Thus, for a worst-case receive bit, one must consider sequences of data and jitter that are of the order of 40 bits long and independent of each other.
A common way to analyze the above-mentioned effects is to use a time domain simulator such as SPICE to model various effects such as jitter, aggressor data patterns, etc. However, the time one can afford to run the simulation is a limiting factor. For example, when three or four variables that can have values of up to 240 are cross product with each other, there are too many combinations of bit patterns to be simulated realistically. Conventionally, deterministic sequences are devised by hand to attempt to find a worst-case in the channel. Then, a pseudo-random data sequence is run to get some estimate of the worst-case data eye. However, this process requires much computation and thus a significant amount of time, and the process does not guarantee that the worst-case will be determined. There are very specific data patterns that will cause the worst case to occur and it there is a deviation from that data pattern, a much bigger worst-case data eye results.